This invention relates to instruction tracing as an input to microprocessor performance analysis, and particularly to generation of instruction traces for vertical microcode not visible within the scope of traditional instruction trace collection.
Microprocessor performance modeling requires assembly-level instruction traces as input. Super-CISC microprocessors have a “vertical microcode” (aka “millicode”) engine to devolve some CISC instructions into a stream of RISC instructions, much in the same spirit as a function call in a high-level programming language. However these millicode instructions are internal to the microprocessor and not apparent to instruction trace-capturing utilities. Consequently, the performance model is forced to “approximate” the specific behavior of the actual millicode routine.